The manufacture of semiconductor chips typically involves the repeated imaging of multiple patterned layers on a wafer. Active devices such as transistors, capacitors etc. are formed in the silicon. Once the devices are formed, they are connected via interconnects. Interconnects consist of contact holes and contact lines. As the speed of the CMOS device increases the RC time delay in the interconnects will have to be reduced. To address the latter, chips that use 0.13 μ and smaller design rules, will be using Cu and low k-ILD (Inter-layer Dielectric) in the interconnect. When Cu is used as the wiring metal, removal of excess Cu from places other than vias and trenches is achieved through CMP process. Cu CMP is critical to the successful implementation of dual damascene interconnect process.
In damascene process, Cu is deposited on interlayer dielectric (ILD), for instance tantalum, that has been patterned for vias and/or for lines. After Cu deposition is completed, the wafer surface is planarized via CMP process. The CMP process is expected to remove Cu from the surface while leaving those in vias and lines in tact as shown in FIG. 1. However, in reality, removal rate (RR) of Cu 1 and ILD 3 or the barrier layer 2 are not the same and dishing of Cu line as shown in FIG. 2 is commonly noticed. Difference in RR of layers 2 and 3 will lead to erosion of ILD 3 layer as shown in FIG. 3a. Dishing leads to thinning of metal lines as shown in FIG. 3b and formation of uneven ILD surface for the next level metal as shown in FIG. 4. The latter could affect focus during photolithography at the next metal level. It is also likely that the dimples in the ILD could leave metal puddles after Cu CMP that could lead to shorts between lines. Thinning of Cu line could lead to thermal loading as well as to higher RC time constant. Consequently chip yield will be affected. It is important to be able to measure metal dishing and dielectric erosion so that appropriate measures can be taken to control and minimize these process excursions.
Prior art that are used to measure/monitor dishing and erosion includes Contact Profilometry, Differential Interferometry, and Spectral Reflectometry. Contact profilometer can damage the surface it is contacting and is slow in providing profile data. Differential interferometry using Nomarski Microscope (NM) is a non-contact approach. NM microscope produces fringes that are contours of constant slope in one direction. There are two difficulties with using an interferometer that produces slope fringes. First, slope fringes are difficult to interpret and second, slope must be measured in two directions to fully reconstruct a surface profile. While profiling a semiconductor wafer surface, NM is prone to errors resulting from fringe fading if one spot is incident on a low reflectivity material and the other on a high reflectivity material. A Nomarski surface profiler is described in U.S. Pat. No. 5,017,012, which is incorporated by reference herein in its entirety. Interferometry based on Michelson's or Linnick microscope generally requires complex fringe analysis and is subject to extreme sensitivity to environmental effects, especially vibration and air turbulence. A combination of contact profilometry and optical profilometry in one system is described in U.S. Pat. No. 5,955,661, which is incorporated by reference herein in its entirety. Use of spectral reflectometer in measuring dishing is described in U.S. Pat. No. 6,464,563, which is incorporated by reference herein in its entirety. In this method, grating structure on the wafer surface is illuminated with polychromatic or white light to generate spectral reflectance profile. Dishing in the process layer is determined using a look-up library composed of several reflectance profiles. The disadvantage of this approach is that it mandates a priori knowledge of layers under the grating in order to compute the library profiles. That requirement effectively excludes doing dishing measurement directly on the device structure in the wafer. Reflectometry technique is not useful in measuring dishing of non-grating structure such as wide metal lines. In another optical approach described in U.S. Pat. No. 6,392,749, which is incorporated by reference herein in its entirety, surface profiling is achieved by measuring either the slope or height of surface features with position sensitive segmented detectors. From the slope information, surface topography can be computed. The technique described therein is capable of measuring either height change or slope change. It uses two laser sources and two quad detectors placed in orthogonal planes to measure surface profile. This approach could suffer from errors resulting from source to source and detector to detector variations. The difference signal from the two detectors needs to be processed further to get the height or slope information. In a patterned wafer with grating like structures, reflectivity in one plane (classical) will be significantly different from that on the other plane (conical). This could give rise to detector saturation and light-level control issues. Another embodiment described in the same patent, uses a single laser source and two detectors. Here two different points on the wafer surface are imaged simultaneously. Once the whole wafer surface is scanned, the two images are digitally shifted and subtracted to obtain height information. This approach again is subjected to detector to detector variability error and any error that is associated with the significant amount of post processing that follows data acquisition.